1. Field of the Invention
The present invention relates to a capacitor and a manufacturing method thereof. More particularly, it relates to the improvement of the capacitance density of a capacitor, reduction of ESL (Equivalent Series Inductance), the improvement of the arbitrariness of the electrode metal and the dielectric material in the configuration of a capacitor, and simplification of the manufacturing process of a capacitor.
2. Description of Related Art
As currently widely used capacitors, Al electrolytic capacitors and multi-layer ceramics capacitors are known. With Al electrolytic capacitors, an electrolyte is used. This entails a difficult problem that a configuration for preventing solution leakage must be considered, or other difficult problems. Whereas, multi-layer ceramics capacitors require sintering. This entails a difficult problem that design allowing for distortion due to a difference in thermal contraction between the electrode and the dielectric substance or the like must be adopted, and other difficult problems. Examples of a technology for implementing a compact large-capacitance capacitor include a grain boundary-insulated semiconductor ceramic capacitor shown in JP-B-61-29133, a capacitor structure and a manufacturing method thereof shown in JP-A-2003-249417.
In JP-B-61-29133, there is disclosed a capacitor which includes a semiconductor grain boundary insulated dielectric substance porcelain including a plurality of through holes extending toward the opposing end faces, electrodes for external connection respectively provided on the opposing end faces of the dielectric substance porcelain, and electrode bodies for capacitance including a high melting point metal inserted through respective through holes of the dielectric substance porcelain. The electrode bodies for capacitance are conductively connected, adjacent ones to mutually different ones of the electrodes for external connection, respectively. Whereas, JP-A-2003-249417 discloses one example of a method for obtaining a capacitor structure body. This method includes the following steps: a thin film formation processing is performed by using a porous substrate obtained from anodic oxidation of a substrate, thereby to form a first electrode including a large number of pillar-shaped bodies regularly formed on the surface of a capacitor substrate; a dielectric thin film is formed on the first electrode so as to cover the outsides of the pillar-shaped bodies; and a second electrode is formed on the surface of the dielectric thin film so as to cover the outsides of the pillar-shaped bodies.
Whereas, in JP-A-09-45577, there is disclosed a method for manufacturing a multi-layer electronic device configured such that a plurality of internal electrodes are disposed so as to oppose each other via a ceramic layer. The method includes a step of forming a metal film on a substrate, a step of forming a prescribed electrode pattern to be internal electrodes by trimming the metal film with photolithography, and a step of forming a ceramic to be a functional element part with a dry plating method in the gap part of the electrode pattern. Further, in JP-T-2006-512787 (the term “JP-T” as used herein means a published Japanese translation of a PCT patent application), there is disclosed a capacitor which includes a first electrode formed on a semiconductor substrate, including a first via and a metal layer connected to the first via, and electrically connected to a first region of the semiconductor substrate; a second electrode formed on the semiconductor substrate, including a second via and a metal layer connected to the second via, and electrically connected to a second region of the semiconductor substrate; and a high-permittivity dielectric substance disposed between the first electrode and the second electrode.
However, the background art described up to this point has the following problems. First, with the technology according to JP-B-61-29133, a semiconductor grain boundary insulated dielectric substance porcelain having a plurality of through holes is used as a dielectric layer, and it is configured such that electrode bodies for capacitance are selectively inserted through the respective through holes. However, micromachining thereof is difficult, which entails a problem that large capacitance due to an increase in area is difficult to attain. Whereas, with the technology according to JP-A-2003-249417, adhesion of the electrode material to the porous substrate used as a mask, an enlargement of the holes due to etching of the porous substrate itself, and the like occur. Therefore, it is difficult to obtain pillar-shaped bodies with a uniform cross sectional shape and a desirable shape. Further, when the pillar-shaped bodies increase in height, a difference in film thickness tends to occur in a dielectric thin film to be formed subsequently. This entails a problem that it is difficult to attain a large capacitance by an increase in height of pillar-shaped bodies.
With the technology according to JP-A-9-45577, the electrode is formed by etching of the metal film formed on the substrate. Therefore, it is difficult to increase the aspect ratio in a z direction (direction of thickness). Whereas, also with the technology according to JP-T-2006-512787, the electrode is formed by etching. Therefore, it is difficult to increase the aspect ratio in a z direction. Thus, unfavorably, with the electrode forming technology by etching, it is difficult to increase the aspect ratio in a z direction of the electrode part, and to increase the area defining the capacitance.